发明名称 |
High density planar SRAM cell using bipolar latch-up and gated diode breakdown |
摘要 |
Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.
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申请公布号 |
US6773968(B1) |
申请公布日期 |
2004.08.10 |
申请号 |
US20000609813 |
申请日期 |
2000.07.03 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
FORBES LEONARD;NOBLE, JR. WENDELL P. |
分类号 |
H01L27/102;H01L27/12;(IPC1-7):H01L21/332 |
主分类号 |
H01L27/102 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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