MEMORY CELL, DESTRUCTIVE READ MEMORY AND METHOD FOR SHORTENING READ OPERATION

摘要

PURPOSE: A memory cell, a destructive read memory and a method for shortening a read operation are provided to reduce the time required in the read operation by alternating a port set used in each clock cycle. CONSTITUTION: A memory address(401) is inputted to a row decoder(403), a PL decoder and a control logic block(407). The row decoder outputs a row selection signal to a WL1 control block(409) and a WL2 control block(411) controlling word lines(WL1,WL2) of a FeRAM memory cell(20) respectively. The PL decoder controls a PL driver(413) controlling a plate line(PL). The control logic block has an additional input like an I/O control signal and a clock(CLK), and has a control signal controlling the WL2 control block and the WL1 control block and the PL driver. The control logic block has a circuit controlling switching from A port to B port and from a clock cycle to a clock cycle, when using an alternating port method.