SEMICONDUCTOR TESTING APPARATUS

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor testing apparatus that reduces errors caused by the variation of delay time that is generated while the amount of delay in a delay circuit is being calibrated for achieving a method for calibrating the delay circuit precisely, and achieves a test by a test waveform and judgment timing using an edge clock that is generated precisely. SOLUTION: A timing circuit 100 is used for the semiconductor testing apparatus. The semiconductor testing apparatus comprises a variation ratio computing circuit 53 for measuring/calculating the variation ratio of the delay time of the delay circuit 12 to be calibrated by providing a ring oscillator 51 for detecting delay time variation incorporating internal delay time variation being calibrated in the delay circuit 12; and a circuit 6 for calibrating the amount of delay for performing correction computing processing with the variation ratio to a measured period by measuring the oscillation period that is oscillated by an oscillation path including the delay circuit 12 to be calibrated in a system. The amount-of-delay setting data obtained by the circuit 6 for calibrating the amount of delay are set to be true calibration amount-of-delay setting data. COPYRIGHT: (C)2004,JPO&NCIPI