发明名称 |
METHOD FOR CREATING AN INTEGRATED SEMICONDUCTOR CIRCUIT COMPRISING A TIMING HIERARCHY, COMPUTER PROGRAM PRODUCT FOR CREATING A TIMING HIERARCHY IN AN INTEGRATED SEMICONDUCTOR CIRCUIT, AND LAYOUT DEVICE |
摘要 |
Disclosed is a method for creating a timing hierarchy in an integrated semiconductor circuit comprising a sequential circuit that is provided with at least two synchronous switching elements with respective timing circuits. The inventive method comprises the following steps: synchronous switching elements having uncritical switching prerequisites regarding a signal arrival time relative to a clock pulse arrival time are determined; the clock pulse arrival time is delayed with the aid of at least one delaying element located in the timing circuit of at least one synchronous switching element having uncritical switching prerequisites so as to minimize the number of synchronous switching elements that simultaneously change the switching mode. |
申请公布号 |
WO2004064477(A2) |
申请公布日期 |
2004.08.05 |
申请号 |
WO2004DE00057 |
申请日期 |
2004.01.16 |
申请人 |
INFINEON TECHNOLOGIES AG;ENDRES, HEINZ;ZETTLER, THOMAS |
发明人 |
ENDRES, HEINZ;ZETTLER, THOMAS |
分类号 |
G06F1/10;G06F17/50 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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