| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce jitters generated in an output clock as much as possible when a PLL circuit formed on a semiconductor chip is used as a clock multiplication circuit. <P>SOLUTION: A power supply line connected to the respective circuit blocks of a reference oscillator, a phase comparator, a charge pump circuit, a frequency divider and an output buffer is separated from a power supply line connected to a voltage controlled oscillator. <P>COPYRIGHT: (C)2004,JPO&NCIPI |
