发明名称 SPACER INTEGRATION SCHEME IN MRAM TECHNOLOGY
摘要 A magneto resistive memory device is fabricated by etching a blanket metal stack comprised of a buffer layer, pinned magnetic layer, a tunnel barrier layer and a free magnetic layer. The problem of junction shorting from resputtered metal during the etching process is eliminated by formation of a protective spacer covering the side of the freelayer and tunnel barrier interface. The spacer is formed following the first etch through the free layer which stops on the barrier layer. After spacer formation a second etch is made to isolate the device. The patterning of the device tunnel junction is made using a disposable mandrel method that enables a self-aligned contact to be made following the completion of the device patterning process.
申请公布号 WO2004032144(A3) 申请公布日期 2004.08.05
申请号 WO2003EP10678 申请日期 2003.09.24
申请人 INFINEON TECHNOLOGIES AG;IBM INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 COSTRINI, GREG;HUMMEL, JOHN, P.;LOW, KIA-SENG;FINDEIS, FRANK;KASKO, IGOR;RABERG, WOLFGANG
分类号 G11B5/127;G11B5/33;G11C11/00;G11C11/15;G11C11/34;H01L21/00;H01L21/331;H01L21/335;H01L21/8232;H01L21/8246;H01L27/105;H01L27/146;H01L27/22;H01L31/0352;H01L43/12 主分类号 G11B5/127
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