发明名称 MULTI-RAIL ASYNCHRONOUS FLOW WITH COMPLETION DETECTION AND SYSTEM AND METHOD FOR DESIGNING THE SAME
摘要 A method for designing a multi-rail asynchronous circuit is provided. The method includes providing a circuit having n circuit paths, defining a plurality of nodes, each node having an n-rail signal output and at least one n-rail signal input, each rail of the n-rail signal input being connected to a different one of the plurality of circuit paths, and adding completeness detection to each of the plurality of nodes, completion detection for a downstream one of the plurality of nodes being at least partially based on completion detection from an upstream one of the nodes. Signals propagate along the plurality of data paths independent of the completeness detection.
申请公布号 WO02091164(A3) 申请公布日期 2004.08.05
申请号 WO2002US14267 申请日期 2002.05.07
申请人 THESEUS LOGIC, INC. 发明人 KONDRATYEV, ALEX
分类号 G06F7/00;G06F17/50 主分类号 G06F7/00
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