| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To uniformly polish an entire wafer in a CMP process before forming transistors. <P>SOLUTION: The method for generating layout patterns includes a step (a) for arranging a primitive cell for indicating each pattern of a plurality of components of semiconductor devices in the region of the semiconductor devices; and a step (b) for arranging at least one fill cell, where each primitive cell has a diffusion layer pattern, and the diffusion layer pattern is provided at a space area in the region of the semiconductor devices after the plurality of primitive cells are arranged. In this manner, the diffusion layer is arranged over the entire wafer and polishing can be uniformly made by the CMP method. <P>COPYRIGHT: (C)2004,JPO&NCIPI</p> |
