发明名称 |
Method and circuit arrangement for memory error processing |
摘要 |
The present invention relates to a method and circuit arrangement for performing an error correction in a memory arrangement in which a redundancy system is used. The addresses of faulty cells are recorded redundantly by applying a corresponding coding. Then, an error correction is applied to the faulty-address information before it is compared to an externally applied address. Thereby, errors due to faulty redundancy addresses can be prevented.
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申请公布号 |
US2004153903(A1) |
申请公布日期 |
2004.08.05 |
申请号 |
US20030481570 |
申请日期 |
2003.12.19 |
申请人 |
DITEWIG ANTHONIE MEINDERT HERMAN;CUPPENS ROGER;SALTERS ROELOF |
发明人 |
DITEWIG ANTHONIE MEINDERT HERMAN;CUPPENS ROGER;SALTERS ROELOF |
分类号 |
G06F11/10;G06F12/16;G11C29/00;(IPC1-7):G11C29/00 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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