| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock data recovery circuit which is easy to analyze a logical system, and regenerates a clock signal which is small in jitters and is stable. <P>SOLUTION: This clock data recovery circuit is provided with a phase comparator which outputs a control signal being a detection result of the phase difference between input data and a clock signal, a charge pump circuit which outputs an error signal corresponding to the phase difference on the basis of the control signal, a loop filter for outputting a controlling voltage level corresponding to the error signal, and a voltage controlled oscillator which changes the oscillation frequency of the clock signal according to the controlling voltage level. Here, the phase comparator comprises: an edge detection circuit for detecting timing where data changes; and a phase frequency comparison circuit which outputs a control signal based on the output of the edge detection circuit and the clock signal. <P>COPYRIGHT: (C)2004,JPO&NCIPI |
