发明名称 |
Semiconductor memory device testable with a single data rate and/or dual data rate pattern in a merged data input/output pin test mode |
摘要 |
Provided is a semiconductor memory device testable with a single data rate (SDR) or a dual data rate (DDR) pattern in a merged data input/output pin (DQ) test mode. The device includes a first path circuit, a second path circuit, and a merged output generator configured to generate a merged data bit having a SDR and/or DDR pattern.
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申请公布号 |
US2004151039(A1) |
申请公布日期 |
2004.08.05 |
申请号 |
US20030748906 |
申请日期 |
2003.12.30 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE JONG-CHEOL;KIM SU-CHUL;CHO UK-RAE |
分类号 |
G11C11/40;G11C29/48;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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