| 摘要 |
PROBLEM TO BE SOLVED: To reduce the whole conductor resistance by preventing the leakage current from increasing by suppressing the spread of a depletion layer upon rectification in a dual semiconductor device, and making the interval between both base regions smaller. SOLUTION: Impurity concentration in an n-type region 121 located just under a separation region IMS1 held between a first end E1 of the first base region 112 and a second end E2 of the second base region 113 is made higher than that in an n-type layer 111 located just under the same region 121, in a first principal surface MS1 of one chip. The depth d of the n-type region 121 is within the depths of the bottom surfaces BS1, BS2. COPYRIGHT: (C)2004,JPO&NCIPI
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