UNIVERSAL POWER CONVERTER

摘要

A universal power converter includes a clock input supplying a delay network for producing a delay at the positive and negative clock transitions and a signal input accepting a pulse width modulated signal, a logic circuitry to combine the delays with the signal so as to produce a low and high limit for the pulse duration of the signal, a shut down logic that protects the output devices from destruction, a second set of delay networks to produce a turn on delay for the output devices, a switched current source to drive the upper output device, a pair of capacitive level shifters driving a pair of gate drive buffers usually with substantially higher operating voltage in order to ensure the full enhanceme nt of the output switching devices without degradation in speed, and a voltage sensor to sample the current across the output device initiating a shut down condition via a monostable multi-vibrator in the even t that safe current limit is exceeded.