发明名称 Fault tolerant computer
摘要 A new method for the detection and correction of errors or faults induced in a computer or microprocessor caused by external sources of single event upsets (SEU). This method is named Time-Triple Modular Redundancy (TTMR) and is based upon the idea that very long instruction word (VLIW) style microprocessors provide externally controllable parallel computing elements which can be used to combine time redundant and spatially redundant fault error detection and correction techniques. This method is completed in a single microprocessor, which substitute for the traditional multi-processor redundancy techniques, such as Triple Modular Redundancy (TMR).
申请公布号 US2004153747(A1) 申请公布日期 2004.08.05
申请号 US20030435626 申请日期 2003.05.06
申请人 CZAJKOWSKI DAVID 发明人 CZAJKOWSKI DAVID
分类号 G01R31/28;G06F11/00;G06F11/14;G11C29/00;H04L1/22;(IPC1-7):H04L1/22 主分类号 G01R31/28
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