发明名称 Multichip module, manufacturing method thereof, multichip unit and manufacturing method thereof
摘要 Reduction of parasitic capacitance originated between semiconductor chip and optical chip by reducing the connection distance thereof by means of interlayer connecting the semiconductor chip mounted on a surface of a resin layer and the optical chip buried on another surface of the resin layer with an interlayer via.
申请公布号 US2004150081(A1) 申请公布日期 2004.08.05
申请号 US20030691382 申请日期 2003.10.22
申请人 OGAWA TSUYOSHI 发明人 OGAWA TSUYOSHI
分类号 G02B6/122;H01L23/02;H01L25/16;H01L31/12;(IPC1-7):H01L23/02 主分类号 G02B6/122
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