| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a delay fixed loop having a wide range of compensative duty error and suppressing the elongation of an initial delay fixed time even if duty compensation increases. <P>SOLUTION: This analog delay fixed loop comprises a delay line 310 for receiving an internal clock and outputting normal and dummy multiphase clocks, a control means 315 for comparing the phase between a reference and the multiphase clock with the delay line 310 and adjusting the delay amount of the delay line 310, an interface 320 for selecting single normal and dummy multiphase clocks out of the output of the delay line, mixing the phases of the both and compensating the duty, the delay line 350 for receiving the mixed clock, a delay model 354 for copying the actual delay value relative to the output, a fine control means 356 for comparing the feedback clock therefrom with the reference and controlling the delay amount of the delay line 350, a control means 370 of the interface 320 and a duty compensation amplification means 360. <P>COPYRIGHT: (C)2004,JPO&NCIPI |
