发明名称 |
MOS transistor and method of manufacture |
摘要 |
A reduced feature size MOS transistor and its method of manufacture is disclosed. The present invention reduces short channel effects but does not include an LDD structure In an illustrative embodiment, a MOS transistor has a gate length of 1.25 mum or less. The exemplary MOS transistor includes a gate oxide that forms a planar and substantially stress free interface with a substrate. As a result of the planarity and substantially stress free nature of the oxide/substrate interface, the incidence of hot carriers, and thereby, deleterious hot carrier effects are reduced. By eliminating the use of the LDD structure, fabrication complexity is reduced and series source-drain resistance is reduced resulting in improved drive current and switching speed.
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申请公布号 |
US2004150014(A1) |
申请公布日期 |
2004.08.05 |
申请号 |
US20040762788 |
申请日期 |
2004.01.22 |
申请人 |
CHAUDHRY SAMIR;SEN SIDHARTHA;CHETLUR SUNDAR SRINIVASAN;GREGOR RICHARD WILLIAM;ROY PRADIP KUMAR |
发明人 |
CHAUDHRY SAMIR;SEN SIDHARTHA;CHETLUR SUNDAR SRINIVASAN;GREGOR RICHARD WILLIAM;ROY PRADIP KUMAR |
分类号 |
C30B33/00;H01L21/265;H01L21/28;H01L21/316;H01L21/318;H01L29/10;H01L29/51;(IPC1-7):H01L29/76 |
主分类号 |
C30B33/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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