Synchronous bus system for minimising clock-data skew - has data bus and clock source feeding clockline with two segments, data travels on data bus in constant phase relationship with clock signal

摘要

The bus system has a topology that minimises clock-data skew. The bus system includes a data bus, a clockline and devices sending data signals to and receiving from the data bus. The clockline has two segments, each segment extending the entire length of the data bus. The segments are joined by a turnaround at one end. Devices in the bus system use one clockline segment as a receive clock and the other as a transmit clock. Synchronisation circuitry is used to send a data signal to the data bus such that the data signal will travel in a constant phase relationship with respect to the clock signal. The synchronisation circuitry synchronises data with the transmit clock of the particular device.