| 摘要 |
<P>PROBLEM TO BE SOLVED: To improve embedding characteristics of the spacing of vertical MISFETs which constitute an SRAM memory cell. <P>SOLUTION: Columnar laminates (P1 and P2), each of which consists of a lower semiconductor layer 57, an intermediate semiconductor layer 58, an upper semiconductor layer 59, and a silicon nitride film 62, are located at a narrow pitch in a Y direction (Y-Y') while being located at a wide pitch in an X direction (X-X'). Therefore, when forming the vertical type MISFETs on top of horizontal type driving MISFET and transfer MISFET, a first insulation film (O<SB>3</SB>-TEOS) 70a having a superior coating property is deposited on top of the columnar laminates and gate electrodes 66 formed on the side walls of these laminates via a gate insulation film, to completely fill the spaces between narrow pitches. Then, a second insulation film (HDP silicon oxide film) 70b is deposited on top of the first insulation film 70a. Consequently, an embedding characteristic of the insulation film can be improved even in a narrow pitch of the vertical MISFETs having a large aspect ratio. <P>COPYRIGHT: (C)2004,JPO&NCIPI |
