LSI alleviating hysteresis of delay time

摘要

A buffer circuit of an LSI includes first inverter and a second inverter cascaded from the first inverter, each of the first and second inverters including a pMOSFET and an nMOSFET. The body areas or backgates of the pMOSFETs operating in opposite phases and body areas of the nMOSFETs operating in opposite phases are respectively coupled together via a coupling line, to thereby prevent hysteresis or fluctuation of the delay time in the operation of the buffer circuit.