| 摘要 |
The conversion processors 1-1-1-4 based on a 4-bit unit are connected in a multistage manner, the number of clocks according to the analog input voltage is counted at each conversion processor 1-1-1-4, and a 4-bit digital signal is obtained. And the surplus voltage in proportion to the length of incomplete clock that is not counted at the conversion processor at the preceding stage is obtained and is transmitted to the conversion processor at the subsequent stage. The 4-bit digital signal obtained at conversion processors 1-1-1-4 is outputted as a 16-bit digital signal via the shift registers 3-1-3-4. Due to this, achieving 4-bit resolution may be acceptable at the individual conversion processors 1-1-1-4, and it is not necessary to cause the clock frequency of the counter 2-1-2-4 to be high. Therefore, while achieving high resolution, the accuracy of A/D conversion can be improved. <IMAGE>
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