发明名称 Type-II all-digital phase-locked loop (PLL)
摘要 System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times. <IMAGE>
申请公布号 EP1443653(A1) 申请公布日期 2004.08.04
申请号 EP20040100122 申请日期 2004.01.15
申请人 TEXAS INSTRUMENTS INC. 发明人 STASZEWSKI, ROBERT B.;LEIPOLD, DIRK;MUHAMMAD, KHURRAM
分类号 H03F1/02;H03F1/32;H03L7/093;H03L7/099;H03L7/107;(IPC1-7):H03L7/107 主分类号 H03F1/02
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