| 摘要 |
A phase noise compensation circuitry is connectible to a reference oscillator (14) which generates a reference signal, affected by phase noise ϕ(t), exploitable either for modulation, demodulation, or simply frequency conversion. The compensation circuitry includes an mixer (17) which receives the reference signal, and a copy of the reference signal after pi /2 phase shifting and delaying by a fixed delay tau spanning an integer number N of periods of the reference signal. The baseband signal at the output of the mixer (17) is proportional to the time derivative of the phase noise voltage. In a preferred embodiment the baseband signal is filtered and A/D converted before reaching a downstream numerical integrator (21) which provides a phase noise estimation voltage proportional to the difference between the phase noise voltage across the delay tau . The delay tau also spans an integer L<N periods of the digital clock: L=1 is the preferred value. The output of the integrator (21), opportunely scaled out, acts as an address ϕ of two look-up tables (23, 24) for obtaining in correspondence respective digital samples sin(ϕ) and cos(ϕ). These digital samples are sent to a complex multiplier (11) which carries out the following digital products: Ð (r)=ÄsI(r).cosϕÜ and Ð (r)=ÄsQ(r).sinϕÜ, in order to perform a digital compensation of the phase noise due to the reference signal. In case the compensation circuit is used by the transmitter the Ð (r), Ð (r) products are In-phase and In-quadrature phase-noise precompensated modulating components. In case the compensation circuit is used by the receiver the Ð (r), Ð (r) products are In-phase and In-quadrature phase-noise postcompensated demodulated components (fig.2). <IMAGE>
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