发明名称 AN ARRANGEMENT AND A METHOD IN PROCESSOR TECHNOLOGY
摘要 A processor (PR2) has a functional unit (FU21) connected to series coupled temporary registers (TR21-TR23) and to a register file (RF2), which has an output connected to an input (IP1) of the functional unit via multiplexors (MUX1-MUX4). Read addresses (B, E, A) and write addresses (A, D, G) are sent to the register file and to a control means. The latter includes registers (REG1-REG4) and comparators (C1-C4) which control the multiplexors (MUX1-MUX4). On a read address (B) a value (V(B)) is sent to the functional unit (FU21) after the register file access time has lapsed. The functional unit performs an operation and the result (V(A)) is clocked through the temporary registers (TR1-TR3) and is sent to the register file (RF2). A later read address (A) coincides in the comparator (C2) with a write address (A) from the register (REG2), the multiplexer (MUX2) is switched and the result (V(A)) is fetched from the temporary register (TR1). The result (V(A)) can already be used, although it is under access in the register file (RF2) and can not yet be fetched from there.
申请公布号 EP1442362(A1) 申请公布日期 2004.08.04
申请号 EP20010977045 申请日期 2001.10.24
申请人 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL) 发明人 LINNERMARK, NILS, OLA
分类号 G06F9/30;G06F9/38;(IPC1-7):G06F9/38 主分类号 G06F9/30
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