发明名称 |
Architecture for reconfigurable digital signal processor |
摘要 |
The present invention relates to digital embedded architecture (1), including a microcontroller and a memory device, suitable for reconfigurable computing in digital signal processing and comprising: a processor (2), structured to implement a Very Long Instruction Word elaboration mode by a general purpose hardwired computational logic, and an additional data elaboration channel (5, 6) comprising a reconfigurable function unit based on a pipelined array (7) of configurable look-up table based cells controlled by a special purpose control unit (8), thus easing the elaboration of critical kernels algorithms. <IMAGE>
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申请公布号 |
EP1443418(A1) |
申请公布日期 |
2004.08.04 |
申请号 |
EP20030425055 |
申请日期 |
2003.01.31 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
CAMPI, FABIO;TOMA, MARIO;LODI, ANDREA;CAPPELLI, ANDREA;CANEGALLO, ROBERTO;GUERRIERI, ROBERTO |
分类号 |
G06F9/38;G06F15/78;(IPC1-7):G06F15/78 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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