发明名称 |
Clock control circuit and method |
摘要 |
A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.
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申请公布号 |
US6771107(B2) |
申请公布日期 |
2004.08.03 |
申请号 |
US20020330275 |
申请日期 |
2002.12.30 |
申请人 |
NEC ELECTRONICS CORPORATION |
发明人 |
SAEKI TAKANORI |
分类号 |
G06F1/10;H03K5/13;H03K5/135;H03K5/14;H03K5/15;H04L7/00;H04L7/033;(IPC1-7):H03K3/00;G06F1/04 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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