| 摘要 |
A data processing apparatus has a main memory and a plurality of memory banks. A bank switching instruction designating a particular bank address of the first memory bank is stored in an arbitrary memory space in the main memory. A main return instruction designating a particular main address of the main memory is stored in the memory address represented by a particular bank address of the nth memory bank. When the bank switching instruction is read, the readout destination is branched to the first memory bank. Data stored in the first memory bank, the second memory bank, . . . , and the nth memory bank are successively read. When the main return instruction is read from the nth memory bank, the readout destination returns to the main memory.
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