Circuit, system, and method for using hysteresis to avoid dead zone or non-linear conditions in a phase frequency detector

摘要

A phase frequency detector (PFD) utilizes hysteresis dead zone avoidance while maximizing the linear range and minimizing the power and area consumed by the PFD circuit. The PFD includes a hysteresis in a reset logic gate, which prevents the reset logic gate from switching its output before each of the corrective pulses from the PFD reach final steady state DC voltage values. The PFD response simulates an ideal response, such that linearity is maintained at the phase lock point and throughout a linear range of +/-2pi. In addition, the hysteresis reset logic gate monitors the corrective pulses to insert an appropriate amount of time delay into the PFD reset path without introducing additional delay elements. As a result, the linear range of the PHD is maximized and the power and area consumed by the PFD is minimized, due to the fact that additional delay elements are eliminated from the design.