| 摘要 |
A bus switch system having an adapter, a first input and first output register in cascade connection on a data transferring bus of bus switch that comprise input and output shift registers. There is also a bridge, the second input and second output registers are in a cascade connection on the first data transferring bus form a shift register. This allows data to be transferred to an adjacent adapter at one clock cycle, thereby the data transfer is made faster. The data transfer on the first and second data transferring buses is conducted in one direction and input/output control is optimally conducted by first and second control means so that switch control in data transfer is made easier.
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