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发明名称
半导体装置及其制造方法
摘要
本发明系提高以低介电常数之SiOC膜构成配线层间膜及通路层间膜之铜镶嵌配线之可靠性。藉由以SiOC膜构成配线层间膜15、23及通路层间膜21之各个,并以SiCN膜A与SiC膜B之层叠膜构成阻挡绝缘膜14、22及封盖绝缘膜20,谋求降低配线层间膜15、23及通路层间膜21之泄漏电流和提高阻挡绝缘膜14、22与封盖绝缘膜20的黏着性。
申请公布号
TW200414283
申请公布日期
2004.08.01
申请号
TW092128712
申请日期
2003.10.16
申请人
瑞萨科技股份有限公司
发明人
大森一稔;田丸刚;大桥直史;佐藤清彦;丸山裕之
分类号
H01L21/00
主分类号
H01L21/00
代理机构
代理人
陈长文
主权项
地址
日本
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