SEMICONDUCTOR MEMORY DEVICE TESTED BY SDR MODE AND DDR MODE AT MERGED DQ MODE TEST PROCESS

摘要

PURPOSE: A semiconductor memory device tested by an SDR(Single Data Rate) mode and a DDR(Double Data Rate) mode at a merged DQ mode test process is provided to test the semiconductor memory device by using the SDR mode and the DDR mode at the merged DQ mode test process. CONSTITUTION: A semiconductor memory device tested by an SDR mode and a DDR mode at a merged DQ mode test process includes a first path part, a second path part, and an integrated output signal generator. The first path part(310) is used for transferring selectively the first inner data, which are outputted, from the first edge block of clock signals. The second path part(330) is used for transferring selectively the second inner data, which are outputted, from the second edge block of the clock signals. The integrated output signal generator(350) is used for outputting integrated output signals of an SDR mode or a DDR mode in response to the outputs of the first and the second path parts.