METHOD FOR FORMING DUAL DAMASCENE INTERCONNECTION PATTERN OF SEMICONDUCTOR DEVICE

摘要

PURPOSE: A method for forming a dual damascene interconnection pattern of a semiconductor device is provided to prevent or minimize a node separation defect by compensating for a peeled part of the upper part of an interlayer dielectric with a hard mask or a trench opening while using a capping layer. CONSTITUTION: The dual damascene interconnection pattern is formed by using the first and second hard masks. After the second opening for extending the first opening of a via is formed as a trench type. Before a via etch blocking layer gets open, a capping layer(30) for compensating for the peeled portion of the upper part of the interlayer dielectric(8) with the second opening is formed.