发明名称 DIGITAL SIGNAL DECODER AND DIGITAL SIGNAL DECODING METHOD
摘要 PROBLEM TO BE SOLVED: To provide a digital signal decoder capable of a high-speed operation with small power consumption. SOLUTION: The digital signal decoder for generating the sequence of binary codes from a convolution-encoded input signal sequence by maximum likelihood estimation is constituted of only an addition, comparison and selection means (122) for comparing (143 for instance) two metric values (M0_0 and M4 for instance) one time before a prescribed branch metric value (BM00 for instance) calculated from the input signal sequence at each time, adding the prescribed branch metric value (BM00 for instance) to the two metric values (M0_0 and M4 for instance) respectively independent of the comparison processing, selecting one (147 for instance) of two added results corresponding to the compared result of the two metric values (output of 143 for instance) and outputting it as the metric value to be used at the next time. COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004214965(A) 申请公布日期 2004.07.29
申请号 JP20020382260 申请日期 2002.12.27
申请人 TOSHIBA CORP 发明人 YAMAKAWA HIDEYUKI
分类号 G06F11/10;G11B20/10;G11B20/18;H03M13/41;(IPC1-7):H03M13/41 主分类号 G06F11/10
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