Frequency locked loop, clock recovery circuit and receiver

摘要

A frequency locked loop comprising a controllable oscillator (1) and a control signal generator (2) for generating a control signal (Sc) for the oscillator (1) from a reference signal (Sref) and an output signal (So) from the oscillator (1). The frequency locked loop is characterized in that, the control signal generator (2) comprises a first chain including a high pass filter (21) and a non-linear processing unit (22) for generating a first intermediate signal (S1) from the reference signal (Sref), a second chain including a high pass filter (23) and a non-linear processing unit (24) for generating a second intermediate signal (S2) from the output signal (So) of the controllable oscillator (1), a combination unit (25) for generating a third intermediary signal (S3) from the first (S1) and the second intermediary signal (S2), a low-pass filter (26) for providing the control signal (Sc) in response to the third intermediary signal (S3).