| 摘要 |
PROBLEM TO BE SOLVED: To provide a device and a method for logic equivalent verification, which can decrease time and effort for mismatching cause analysis after logic equivalent verification and reduce design/verification TAT. SOLUTION: The logic equivalent verification device performs logic equivalent verification for two circuits and displays results of the logic equivalent verification. In each logic corn of the two circuits that correspond each other, the logic equivalent verification device has a preprocessing means 7, which performs structure matching to determine whether or not there are any corresponding parts in the circuit structures, an internal DB 5, in which results of the structure matching are recorded as an identifier for every element, and a sub corn extraction means 8, which extracts an element group, the elements of which are connected each other and have the same identifier, from logic corns as a sub corn. In addition, the logic equivalent verification device also has a verification means 9, which performs logic equivalent verification for the two circuits for every extracted sub corn, and a display control means 10, which displays only sub corns that the results of logic equivalent verification are mismatched. COPYRIGHT: (C)2004,JPO&NCIPI
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