发明名称 |
Accelerated scan circuitry and method for reducing scan test data volume and execution time |
摘要 |
An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).
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申请公布号 |
US2004148554(A1) |
申请公布日期 |
2004.07.29 |
申请号 |
US20040750949 |
申请日期 |
2004.01.05 |
申请人 |
ON-CHIP TECHNOLOGIES, INC. |
发明人 |
DERVISOGLU BULENT;COOKE LAURENCE H. |
分类号 |
G01R31/3183;G01R31/3185;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/3183 |
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地址 |
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