发明名称 |
System and method for compensating for supply voltage induced clock delay mismatches |
摘要 |
Various systems and methods providing signal delay compensation for circuits such as a multi-pair gigabit Ethernet transceiver are disclosed. In an analog implementation a buffer with an adjustable delay may be used to minimize the delay mismatch between clock trees. The delay of the adjustable-delay buffer is controlled by bias voltages that determine the charging and discharging current to the adjustable buffer. A phase detector circuit is used to compare the clock phases for rising and falling edges, and to adjust the bias voltages that control these edges. In a digital implementation a selector switch, responsive to a phase detector, may be used to route clock signals through circuit elements to delay clock signals.
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申请公布号 |
US2004145397(A1) |
申请公布日期 |
2004.07.29 |
申请号 |
US20040760077 |
申请日期 |
2004.01.16 |
申请人 |
LUTKEMEYER CHRISTIAN A.J. |
发明人 |
LUTKEMEYER CHRISTIAN A.J. |
分类号 |
G06F1/10;G06F3/00;H03L7/081;H03L7/087;(IPC1-7):H03L7/06 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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