发明名称 SYSTEM AND METHOD FOR PACKAGING ELECTRONIC COMPONENTS
摘要 A capacitor design, which incorporates a material set that is adaptable to standard substrate or electronic packaging fabrication methods, uses copper as a base and electrode, mesoporous nanocomposite materials or other adhesion promoting materials combined with a high dielectric material specific to the application's capacitance requirements. This capacitor is then used as a basis for forming a capacitor in substrate or package or wafer level package or die or wafer.
申请公布号 WO2004064464(A2) 申请公布日期 2004.07.29
申请号 WO2004US00181 申请日期 2004.01.06
申请人 VRTIS, JOAN, K. 发明人 VRTIS, JOAN, K.
分类号 H01L23/50;H01L23/538 主分类号 H01L23/50
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