| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a built-in self test (BIST) network using a hierarchy of a universal BIST scheduler (UBS) for scheduling and coordinating testing of elements such as regular structure BIST (RSB) elements and random logic BIST (RLB) elements. <P>SOLUTION: Individual UBSs are preferably positioned in local areas, or sections, of an integrated circuit for testing of RSB elements and RLB elements within the local area. Relatively-short interconnect routing is employed between BIST elements in the tests on the RSB and RLB elements in the local area so that the BIST network can inhibit the delay and clock skew effect to the minimum. Each of the individual UBSs is controlled by a master UBS (MUBS) via simplified timing of control signals. The MUBS also may interface with an external testing device which initiates BIST testing. <P>COPYRIGHT: (C)2004,JPO&NCIPI</p> |
