发明名称 PLL CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a PLL circuit which can realize a PLL oscillator that can reduce the phase noise, due to reference leakage being fully suppressed and a loop band can be set in a wide band to the limit. <P>SOLUTION: The PLL circuit has a phase comparator 1, a 1st charge pump circuit 2, an LPF3, a VCO4, and a frequency divider 5, and the PLL loop formed. Furthermore, the PLL circuit comprises a 2nd charge pump circuit 6 which converts an error signal outputted from the phase comparator 1 into a current, and a control circuit 7a which compares the output of the 2nd charge pump circuit 6 with a reference value, if the output is larger than the reference value, and gradually decrease each output of the charge-pump circuit 2 and the charge-pump circuit 6, until the output becomes lower than the reference value. <P>COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004215105(A) 申请公布日期 2004.07.29
申请号 JP20030001474 申请日期 2003.01.07
申请人 SEIKO EPSON CORP 发明人 GOTO KENJI;KASAI JUICHI
分类号 H03L7/093;H03L7/107;H03L7/18 主分类号 H03L7/093
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