MOS TRANSISTOR

摘要

PROBLEM TO BE SOLVED: To provide an FET device in which the gate activity, line resistance and S/D extension resistance are improved. SOLUTION: A method for manufacturing a semiconductor transistor device is provided with following steps: a semiconductor substrate is formed; the semiconductor substrate has a gate dielectric layer on its surface; lower gate electrode structure is formed on the surface of the gate dielectric layer and the lower gate electrode structure has a low gate upper surface; a planarized layer is formed on the gate dielectric layer so that the upper part of the lower gate electrode structure is left in an exposed state; upper gate structure is formed on the lower gate electrode structure to form a T-type gate electrode; the lower surface of the upper gate structure and the vertical sidewall of the gate electrode are exposed; the planarized layer is removed; a source/drain extension is formed in the substrate protected from a short channel effect; a sidewall spacer is formed adjacent to the exposed lower surface of the upper gate and the exposed vertical sidewall of the T-type gate electrode. A source/drain region is formed in the substrate. A silicide layer is formed on the upper part of the T-type gate electrode and the upper part of the source/drain region. COPYRIGHT: (C)2004,JPO&NCIPI