发明名称 |
Memory system for a multibus architecture |
摘要 |
A memory system connected to several buses (P, DO, D1) for multifunctional data coupling has a sequencing switch (SW) for multiplexing logic arbitration between alternate processors attached to a unified data flow connection (B). Pause signals are communicated via a pause signal circuit (STL) to a sequence control device capable of avoiding interference between simultaneous data flow sequences.
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申请公布号 |
EP1441359(A1) |
申请公布日期 |
2004.07.28 |
申请号 |
EP20030030003 |
申请日期 |
2003.12.31 |
申请人 |
MICRONAS GMBH |
发明人 |
HERZ, RALF;NOESKE, CARSTEN |
分类号 |
G11C7/10;(IPC1-7):G11C7/10;G06F13/16;G06F13/40 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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