发明名称 |
Timing signal generation circuit and semiconductor test device with the same |
摘要 |
A timing signal generation circuit comprising: a negative feedback loop comprising; a variable delay circuit for outputting a timing signal delayed from an input clock signal by a delay amount designated by a delay code; a phase difference detector for detecting a phase difference between the timing signal and the input clock signal to output a detection signal; and a loop filter for smoothing a waveform of the detection signal to generate a voltage signal and for feeding the voltage signal back to the variable delay circuit: and a cancel unit for generating a reverse detection signal based on the delay code to cancel the phase difference caused by a change in the delay amount where the reverse detection signal is supplied to the low pass filter.
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申请公布号 |
US6768360(B2) |
申请公布日期 |
2004.07.27 |
申请号 |
US20010948503 |
申请日期 |
2001.09.06 |
申请人 |
ADVANTEST CORP. |
发明人 |
TSURUKI YASUTAKA |
分类号 |
G01R31/3183;G01R31/319;H03K5/00;H03K5/13;H03L7/081;(IPC1-7):H03L7/00 |
主分类号 |
G01R31/3183 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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