Two-part memory address generator

摘要

A memory address generator for a multiport data communication system storing received data packets in a memory having a plurality of storage areas. The data communication system has a plurality of receive ports receiving the data packets and a queue of addresses of a plurality of storage areas in the memory available for storing the received data packets. The address generator generates memory addresses to store the received data packets in the plurality of storage areas of the memory and includes first and second registers. The first register receives an address from the queue of addresses and provides a first part of the memory address, and the second register counts write cycles to the memory and provides the count result as a second part of the memory address.