发明名称 Semiconductor memory device with internal clock generation circuit
摘要 A repeater receives an internal clock distributed from a DLL circuit irrespective of a data reading operation and outputs a DLL clock to a data output circuit and a data strobe signal output circuit in response to an internal signal only in the data reading operation. The data strobe signal output circuit receives the internal clock and the DLL clock, generates a data strobe signal in synchronization with the internal clock, and outputs the generated data strobe signal in synchronization with the DLL clock. As a result, a semiconductor memory device attains further reduction of power consumption during active-standby and a secure supply of the internal clock to a prescribed circuit.
申请公布号 US6768698(B2) 申请公布日期 2004.07.27
申请号 US20020255667 申请日期 2002.09.27
申请人 RENESAS TECHNOLOGY CORP. 发明人 KONO TAKASHI
分类号 G11C11/407;G11C7/22;G11C8/18;G11C11/4076;G11C11/409;H03K5/13;(IPC1-7):G11C7/22 主分类号 G11C11/407
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