发明名称 |
Method and arrangement for layout and manufacture of gridded non manhattan semiconductor integrated circuits |
摘要 |
The present invention introduces several methods for implementing non Manhattan routing systems for integrated circuit manufacture. In one embodiment, a non Manhattan routing system is implemented by memorizing where intersections between wiring pitch grids occur and connecting such intersections with vias. In another embodiment, a gridless non Manhattan routing systems may be implemented by adapting a gridless Manhattan routing system by rotating a plane of a tile based maze router.
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申请公布号 |
US6769105(B1) |
申请公布日期 |
2004.07.27 |
申请号 |
US20010972452 |
申请日期 |
2001.10.05 |
申请人 |
CADENCE DESIGN SYSTEMS, INC. |
发明人 |
TEIG STEVEN;CALDWELL ANDREW |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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