| 摘要 |
A method and system are disclosed for a DRAM having a single stage sensing architecture. In this architecture during a Read operation, in any datapath connecting a memory cell to a data I/O, there is one and only one sense amplifier. This sensing and latching scheme allows for the fast execution Read, Write, Write-back, and Refresh operation. Depending on the embodiment, Read and Write-back operations are executed in one, or two, cycles. Multiplexing of arrays and bit-linens results in efficient use of chip area.
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