PROGRAMMABLE MEMORY ARRAY STRUCTURE INCORPORATING SERIES-CONNECTED TRANSISTOR STRINGS AND METHODS FOR FABRICATION AND OPERATION OF SAME

摘要

A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer, preferably connected together by way of vertical stacked vias.