| 摘要 |
<P>PROBLEM TO BE SOLVED: To minimize phase jumps that occur when lines are switched in a clock supply circuit for selecting one from among a plurality of line clocks and obtaining a clock synchronizing the selected line clock. <P>SOLUTION: A clock is extracted from a line 1 to obtain a clock of 8k(x) through a frequency divider. Similarly, a clock is extracted from a line 2 to obtain a clock of 8k(y) through a frequency divider. When a selector 7 selects the clock of 8k(x) as reference, the selected clock of 8k(x) is inputted to a PLO circuit and a synchronous clock is outputted from a VCO 9. The clock is subjected to frequency dividing to generate a reset pulse. The clocks 8k(x) and 8k(y) are maintained in a state in which the clocks of 8k(x) and 8k(y) are close to the same phase by inputting the reset pulse to the frequency divider 6 of the clock of 8k(y) side. A phase jump becomes minimum even when the selector 7 switches references in this state. <P>COPYRIGHT: (C)2004,JPO&NCIPI |
