| 摘要 |
<P>PROBLEM TO BE SOLVED: To solve the following problem that the conventional data receiving circuit (clock reset circuit) has a large latency of a feedback system, so that a feedback circuit of a high cutoff frequency is hard to produce. <P>SOLUTION: The clock reset circuit has boundary detection circuits 20-23 detecting a boundary in an input signal in accordance with a first signal, and performs reset of a clock by controlling the timing of the first signal in accordance with the detected boundary. The clock is so constituted as to be recovered by using a plurality of feedback paths (10-13, 20-23 → 31 → 5 → 6 → 72 → 74 → 75 → 42; 10-13, 20-23 → 71 → 73 → 76 → 74 → 75 → 42) of different signal delays. <P>COPYRIGHT: (C)2004,JPO&NCIPI |
